About Me
Detail-oriented VLSI Design Verification Engineer with hands-on experience in System Verilog, UVM-based verification, and digital design validation. Skilled in developing testbench architectures, performing functional verification, and validating complex digital designs using industry-standard protocols like APB, AXI Lite, SPI, and I2C. Strong understanding of coverage-driven verification, debugging, and simulation workflows. Seeking to contribute to high-performance semiconductor design teams.
Skills & Technologies
Projects
Synchronous FIFO Verification using UVM
Developed a UVM-based testbench architecture including driver, monitor, scoreboard, and sequencer. Performed functional verification of FIFO design under normal, boundary, and corner-case scenarios. Verified data integrity, FIFO ordering, full/empty flags, and reset conditions. Improved design reliability through structured debugging and simulation analysis.
Dual Port RAM Design and Verification
Designed Dual Port RAM using Verilog HDL and simulated using Synopsys VCS. Enabled simultaneous read/write operations for improved memory performance. Validated functionality through simulation and waveform analysis.
Synchronous & Asynchronous FIFO Design
Designed FIFO buffers for reliable data transfer between clock domains. Implemented logic for overflow, underflow, full, and empty conditions, ensuring proper synchronization and data handling.
Education
B.Tech
Electrical and Electronics Engineering
Diploma
Electrical and Electronics Engineering