About

Physical Design trainee with a strong foundation in the RTL-to-GDSII flow using Cadence Genus and Innovus. Skilled in multi-macro floorplanning, port placement, power planning, placement, CTS and routing on complex designs with rectilinear block shapes.

Experience2

1. V(

   Physical Design Trainee

   Jun 2026 — Present

   VLSIMINDS (A Division of S2C Semiconductors Pvt. Ltd.) · Bengaluru

   Working on the RTL-to-GDSII flow for a 28nm design with ~60K cells, 48 macros, and rectilinear block shapes using Cadence Genus and Innovus. Automated port creation and placement with Tcl scripts, handling floorplanning, macro placement, and power planning for the design.

   • Automated port creation and placement with Tcl scripts, reducing congestion at the block boundary
   • Handled floorplanning and macro placement for a 48-macro design
2. V(

   Intern – Physical Design

   Feb 2026 — Apr 2026

   VLSIMINDS (A Division of S2C Semiconductors Pvt. Ltd.) · Internship · Bengaluru

   Completed the synthesis-to-signoff flow for SRAM Memory (45nm) using Cadence Genus and Innovus, achieving timing closure and DRC/LVS compliance. Involved in top-level floorplanning and macro placement for Chip-Top Integration, GPRS.

   • Achieved timing closure and DRC/LVS compliance for SRAM Memory design
   • Conducted top-level floorplanning and macro placement for GPRS design

Projects2

• PicoX32

  Extended PicoRV32 RISC-V core, published at ETFI 2026.

  • Vivado

• MPPT System

  Published at ICESC 2025.

  • MATLAB Simulink

Education3

• SM

  Bachelor of Engineering

  2022 — 2026

  Shri Madhwa Vadiraja Institute of Technology & Management

  Electronics & Communication

• JG

  Pre-University

  2020 — 2022

  Jnana Ganga Pre-University College, Udupi, Karnataka

• GC

  SSLC

  2022

  Government Composite High School, Udupi, Karnataka

Certifications4

• VLSI Design Flow: RTL to GDSII

  NPTEL

• Python for Data Science

  NPTEL

• C Programming

  CodeChef

• Value Added Course

  NGSpice